1. Field of the Invention
The present invention relates to a hazard check method and a hazard check device for checking logic circuit hazards, as well as to a circuit conjunctive normal form (also called CNF) generating method and circuit CNF generating device for generating circuit conjunctive normal forms utilized in hazard check devices and hazard check methods.
2. Description of the Related Art
Systems for generating logic circuits from functions written in hardware terminology are capable of generating circuits just as described in the hardware terminology. However these systems do not take glitches into account during logic optimizing. Synthesizing paths with exceptional timing such as asynchronous paths and multi-cycle paths causes glitches and a hazard occurs when these glitches are conveyed at the timing for inputting data to the flip-flop data, so that the circuit (mistakenly triggers) operation is defective. Moreover, no method was available for detecting these hazards.
The following is a typical case where a hazard is generated at an exceptional timing. First of all, as shown in FIG. 2, a control signal (strobe signal) is installed for controlling whether or not to input data from an exceptional timing path. When that control signal is 0, nothing is input since that exceptional timing path was not set. Conversely, when the control signal is 1, the signal is input. The circuit in FIG. 2 is designed so that no changes in asynchronous paths and multi-cycle paths will ever be conveyed to the flip-flop when that control signal is 0.
However, systems for synthesizing logic circuits might include the circuit of FIG. 3. This circuit is logically identical to that in FIG. 2; however, this circuit conveys data changes caused by effects from the exceptional timing path to the flip-flop even when the control signal is 0. When these changes occur, the flip-flop clock signal (pulse) rises and causes faulty logic circuit operation (hazard).
Technology for checking these type of hazards was disclosed for example in Japanese Unexamined Patent Publication No. JP 2(1990)-112773A for selecting a logic gate from among the logic gates in the digital circuit for a hazard check, and then making a hazard check using judgment criteria described in the hazard generating conditions for that gate.
Also as disclosed for example in Japanese Unexamined Patent Publication No. JP 5(1993)-35816 A, the input conditions in a simulation for detecting a hazard include not only “0” and “1”, but “x” which is neither “0” nor “1”, or in other words is an unfixed level.
Technology was also disclosed for example in, “Fast Hazard Detection in Combinational Circuits”, by C. Jeongand S. M. Nowick, in In Proc. of Design Automation Conference 2004, pp. 592-595 where in FIG. 1, the signal states for inducing a hazard are six types other than 0 and 1.